Drag to orbit, scroll to zoom. Build up the assembly stage by stage, peel it inner-to-outer, pack the interior with rhombic dodecahedra, and move the operating point to see what the physics does. Every readout below the viewer is computed live from the Span–Wagner equation of state.
Layers are ordered by radius. Drag the two handles toward each other to isolate a single shell.
Conventional shows the same silicon as Threadripper-class nodes with four PCIe cards each — the Natas build, repeated as many times as it takes.
The liner and the module are the same solid, so a perfectly-filled vessel is the set of lattice sites lying inside a rhombic dodecahedron. Those counts are 19, 93, 279, 617 — and nothing in between. At any other diameter the outer layer is partly filled: more volume, no more modules. The module itself never changes: one 50 mm rhombic dodecahedron, one die, one bill of materials, at every size.
Density is quoted on the outside of the vessel, not the bore, and includes the modules and the charge. At these pressures the wall is 22–98 mm of Cu-Cr-Zr, so quoting kW per litre of bore hides most of the machine.
The first three tiers are the same machine. 688, 610 and 625 kW/m³ — the spread is noise, so choosing between 19, 93 and 279 modules is a question of what you can move and feed, not of efficiency. All three move on a 4,000 lb cart; the first two clear a single 32″ leaf, the 279 needs double doors at 36″.
On two coils the top tiers cannot be filled — 250 of 279, and only 372 of 617, because above 279 modules the count is pinned by heat rejection rather than by geometry. Four coils removes that limit entirely. Two counter-wound pairs, quarter of a turn apart, take every tier to 100% seated:
| bore | seats | ×2 | ×4 | kW/m³ |
|---|---|---|---|---|
| 326 | 19 | 19 | 19 | 642 → 657 |
| 546 | 93 | 93 | 93 | 631 → 669 |
| 764 | 279 | 252 | 279 | 617 → 691 |
| 984 | 617 | 375 | 617 | 430 → 708 |
Above 617 even four coils cannot fill the vessel. The geometry keeps producing clean clusters — 1163, 1957, 3055, 4497, 6339, all confirmed against the lattice — but the fraction that can be powered falls away monotonically and takes density with it:
| bore | seats | ×4 | fill | kW/m³ | t |
|---|---|---|---|---|---|
| 1203 | 1163 | 969 | 83% | 622 | 6.1 |
| 1423 | 1957 | 1293 | 66% | 496 | 10.3 |
| 1642 | 3055 | 1596 | 52% | 394 | 16.0 |
| 1861 | 4497 | 1901 | 42% | 322 | 23.2 |
| 2081 | 6339 | 2215 | 35% | 269 | 32.4 |
A 2,081 mm bore seats 6,339 modules and can run 2,215 of them — 2.1 MW in a 2.5 m, 32-tonne sphere at 271 kW/m³, which is worse per cubic metre than the 326 mm desk unit. Rejection scales with surface area and demand with volume, so past 984 mm the vessel is buying seats it cannot switch on. 984 mm on four coils is the largest fully-powered machine this architecture makes. Going beyond it needs a different rejection path — more coil circuits, or a remote exchanger — not more vessel.
Four coils is never overkill, even where two would already fill the vessel. More contact strip lets the junction run cooler; a cooler junction means a lower isochore pressure at fault, a lower pressure rating and a thinner wall. On the Business tier that chain is 82 °C → 73, 420 bar → 370, a 50 mm wall → 43, and 153 lb of shell removed — bought with 9 m of extra tube. The Personal tier, which two coils already fills, still sheds 13 lb and gains 15 kW/m³. The only real cost is plumbing: 22 cross fittings instead of 7.
The direction reverses with the second pair. On two coils density collapses past 279; on four it rises with size, 657 → 708 kW/m³, because the vessel is back to being geometry-limited. Junction temperature falls too — 82 °C to 73 at the 546 bore — since the same heat leaves through twice the contact strip. The second pair feeds the top of the receiver: both runs leave their tangency points and climb to one apex, the chord between them closing the triangle.
Note what does not happen. Shells do not fill in order of distance, because the liner is not a sphere. At 548 mm the r²=14 sites are skipped entirely while the more distant r²=16 sites do seat — they point at the rhombic dodecahedron's axis vertices, where there is room. And 654 mm, which shows the highest raw density of any size, is 141 complete plus 24 of 36 — a half-filled shell, so every module in that outer layer has an incomplete lattice neighbourhood.
Hollow keeps only the outer shell, so every module seats on the faceted liner — the motherboard. Interior modules touch nothing and cannot be wired to it.
2 is JEDEC 2-channel (clamshell) mode — the same trick the 96 GB card uses. 3 is not a GDDR7 configuration.
Silicon would allow 3 GB GDDR7 ×14 at maximum overclock; the cooling usually allows less.
Four coils — two counter-wound pairs, one per lid port. Not an option: the top tier cannot be filled without them, and on the small tiers they buy a cooler junction, a lower fault pressure and a thinner wall.
Moving any slider resets everything below it to its most permissive value.
The coil is counterflow: coolant enters cold at the bottom and leaves warm at the top, against the film descending inside. Each turn is drawn at its own temperature.
A rhombic dodecahedron has 14 vertices — 8 cube corners and 6 axis points — so 14 sealed pockets with the fibre passing through. Memory sits on the 12 faces instead: the RD is face-transitive, so all twelve pockets are one size and one assembly, and 12 × 16 = 192 — exactly the 6 dies × 32 devices a 512-bit interface can address.
The die is a hollow cube of six reticle-limited dies, joined edge to edge with their active faces inward on a common cavity and their reverse faces outward to the fluid. Every die keeps a direct path to the coolant — a vertical stack buries its inner members. Six of them are one hop from each other.
The 14 pockets land on that cube exactly: 8 at its corners, 6 at its face centres. Componentwise sign() maps every pocket to its own site with none left over, because the RD's vertices are a cube plus an octahedron. That correspondence is the reason for the shape.
The three modules, locked. Each is sized by the bus its silicon can address, not by how densely packages fit — filling a pocket past the bus buys chips with nowhere to connect.
| module | cubit | sites | chips | cap |
|---|---|---|---|---|
| GPU | 16 GDDR7 | 12 | 192 | 576 GB |
| CPU | 24 DDR5 | 20 | 480 | 6 TB |
| SSD | 16 NAND | 12 | 192 | 384 TB |
GPU 192 = 6 dies × 32 (512-bit clamshell), every chip data. CPU 480 = 384 data + 96 ECC, the four ECC cubits on one tetrahedron of the eight corner sites — the only split that hits 4:1 exactly. NAND carries no ECC chips: it is inside the part, spare area plus LDPC.
14 × 3 GB = 42 GB against the reference card's 96 GB over 32 sites. A capacity loss — but this module was always a latency play. All 12 faces are equidistant from the die, so no board sits further from it than any other.
Verified against NVIDIA RTX PRO 6000 Blackwell: GB202 ~750 mm², 600 W board, 96 GB GDDR7 across 32 sites, 512-bit, 1792 GB/s. The die must fit the largest square inscribable in a rhombic face (0.586·R), which puts the module floor at 50 mm.
Every figure is graded. [M] derived in this model, [P] published third-party, [A] assumption. Present the [A] rows as assumptions or not at all.
A cross-node traverse in a data centre passes GPU → PCIe root → NIC → cable → switch → cable → NIC → PCIe → GPU. Ours passes none of them.
| Stage | Data centre | ChipVat | Grade |
|---|---|---|---|
| Switch forwarding | < 100 ns | none | [P] |
| NIC + PCIe, each end | ~500–1000 ns | none | [A] |
| Cable, across a row | 152 ns | none | [A] |
| Longest internal path | — | 600 mm = 2.4 ns | [M] |
| Small-message end to end | ~1.5–2 µs | ~200 ns | [A]/[M] |
Conservatively 7× to 10× lower cross-die latency, allowing 200 ns of SerDes on our side. This is the strongest claim and the hardest to answer.
[P] 575 W is the air-cooled board power of an RTX PRO 6000. [M] 806 W per die is what this cooling removes — 140 %, held continuously rather than as a boost window.
⚠️ Performance does not scale linearly with power. At exponents of 0.5–0.7 that is 1.18× to 1.27× per-die throughput. Quote the watts as fact and the throughput as a range — or benchmark it before claiming a number.
The working fluid is the dielectric. By Clausius–Mossotti at 800 kg/m³, ε = 1.462 gives 0.827 c against FR-4's 0.482 c. [M]
It compounds with distance: 43 dies sit within 600 mm of each other, so the entire machine is inside the cable length a data centre spends reaching the next rack.
43 dies, 16.5 TB, 34.7 kW, 372 kg, 1.27 × 0.64 m on one platform truck. [M]
The largest movable conventional unit is a four-GPU workstation. This is 10.8× the dies of anything you can currently wheel, and conventionally the same die count is about eleven towers — a populated rack, which does not move.
The right question is how much room it takes to match one machine deployed for real — not how big the bare hardware is.
| ChipVat | 43 dies conventionally | |
|---|---|---|
| Hardware | 1 cart | 6 servers, 2 racks |
| Floor, bare | 0.81 m² | 1.44 m² |
| With aisles / clearance | 1.63 m² | 5.00 m² |
| CRAC + chiller + UPS | none | 4.29 m² |
| Total floor | 1.63 m² | 9.29 m² |
| Total volume | 0.81 m³ | 27.9 m³ |
5.7× the floor, 34.3× the volume. And the ChipVat figure is a cart — it rolls out of the room. The conventional figure is a fitted-out data hall.
Rack allocation 2.5 m² is dense-colocation practice; typical enterprise is 3.5 m², widening the gap to 7.7×. Cooling-plant areas are estimates [A] and should be replaced with site quotes.
[P] Uptime Institute 2025: weighted average PUE 1.54 — 54¢ of overhead on every dollar of compute, and unchanged for six consecutive years. Hyperscale reaches 1.10–1.15; colocation and enterprise sit at 1.58–1.80.
We reject heat at the bulk temperature, 60–88 °C. A dry cooler works against ambient at that temperature almost anywhere, almost all year. Conventional racks reject at ~35 °C and need mechanical chillers — which is where the 54 % goes. [A] our overhead is a circulation pump and dry-cooler fans, no chiller, no CRAC, no air handling: PUE ≈ 1.08.
| Facility | PUE | Total | Overhead | vs ours |
|---|---|---|---|---|
| Hyperscale best | 1.12 | 38.9 kW | 4.2 kW | +1.4 kW |
| Industry average | 1.54 | 53.4 kW | 18.7 kW | +16.0 kW |
| Colo / enterprise | 1.70 | 59.0 kW | 24.3 kW | +21.5 kW |
| ChipVat | 1.08 | 37.5 kW | 2.8 kW | — |
139,827 kWh a year avoided on one machine — entirely cooling overhead:
| Electricity | Industry avg | ChipVat | Saving / year |
|---|---|---|---|
| $0.08 US industrial | $37,449 | $26,263 | $11,186 |
| $0.13 US commercial | $60,855 | $42,678 | $18,178 |
| $0.22 California | $102,986 | $72,224 | $30,762 |
At 10 MW of compute the gap is 4.6 MW of cooling plant — $3.2 M/year at $0.08, $8.9 M/year at California rates.
And a second effect: heat leaving at 60–88 °C is district-heating grade. Conventional 35 °C return water is not worth recovering. The rejected heat becomes a product rather than a disposal cost.
Per-die the hardware is heavier and thirstier than a tower — 1.25× the power and 1.63× the mass for the same die count. That is a component-level comparison; the deployed-space comparison above is the one that decides purchases, but expect the component figure to be raised. [M]
35 kW at the wall for a movable unit, and 372 kg needs a 2000 lb platform truck, not a hand cart. [M]
Memory fusion buys capacity, not bandwidth — the bus still sees 32 devices. [M]
The PUE 1.08 is an estimate, not a measurement. It assumes a dry cooler suffices year-round at your site's ambient. In a hot climate, or if the loop needs any mechanical chilling, the advantage narrows toward the hyperscale 1.12 rather than the 1.54 average. [A]
Nothing is off-the-shelf. The shell alloy, the module, the substrate and the packaging are all novel manufacture. [A]
Three of these came out of building the geometry. The packing result is new — it falls out of the fact that rhombic dodecahedra tile space on an FCC lattice, and a regular dodecahedron is not an FCC cell.
Rhombic dodecahedra tile space perfectly — but on the FCC lattice, whose twelve nearest neighbours point at the vertices of a cuboctahedron. A regular dodecahedron's twelve faces point somewhere else entirely. The two twelves are not the same twelve.
So RD modules mounted one-per-facet on a dodecahedral liner are not in contact with each other the way RDs naturally pack. Slide the shell count past 1 and watch it: the interior fills on the FCC lattice, and those positions ignore the liner facets.
This is worth a claim either way. The self-similar option — an RD-shaped liner holding FCC-packed RD modules — nests exactly, every module face mates with a neighbour or the wall, and the interconnect substrate becomes the same polyhedron at two scales. Nothing filed describes that.
Closing the thermal loop changed the story. Internal convection is not the constraint — the film can carry about 6.9 W/cm² and a realistic build asks for barely 2. The constraint is getting that heat out through the wall.
A helical coil on a 416 mm vessel touches roughly 0.11 m² of shell. The shell's whole surface is 0.65 m². So the coil sees about a sixth of the available area, and with a coolant-side film and the wall conduction in series that works out near 120 W/K.
| Per module | 13 modules | Bulk | Die | Verdict |
|---|---|---|---|---|
| 120 W | 1.6 kW | 31 °C | 33 °C | comfortable |
| 350 W | 4.6 kW | 58 °C | 69 °C | near the limit |
| 600 W | 7.8 kW | 83 °C | 101 °C | over junction limit |
So this vessel is a 4–5 kW machine as drawn, not a 15 kW one. Getting past that needs rejection area: more coil, external fins, or a remote exchanger.
Correction to what I said a moment ago: I claimed a jacket would give roughly 20× the area. It does not. Against a coil with realistic fin spreading it is 2.1×, and it barely moves the answer — because the coil is not the dominant resistance either.
The dominant resistance is the pressure wall. At 500 bar the ASME thickness is 39 mm, and 39 mm of steel at 16 W/mK accounts for 88 % of the total. At 896 mm and 84 mm of wall it is 94 %. You cannot fix that with a better heat exchanger on either side of it.
Two things follow, and the second one is the important one:
| Route | UA | Effect |
|---|---|---|
| Coil, as drawn | 130 W/K | baseline |
| Full jacket (blocked by SuCCoR) | 276 W/K | 2.1× |
| Perfect external sink | 314 W/K | the wall's own ceiling |
| Drop rating 500 → 250 bar | 217 W/K | 1.7×, from wall thickness alone |
So being locked out of the jacket costs you about a factor of two, not the disaster I implied. And lowering the pressure rating buys nearly as much as the jacket would — the film has 5× margin it is not using, so charge density is not what needs protecting.
Wall thickness grows with radius, so U falls as 1/R while area grows as R². Rejection therefore scales linearly with vessel radius while volume scales as the cube. Every doubling in size leaves the tank emptier.
| Vessels | Each ID | Total UA | Total volume |
|---|---|---|---|
| 1 | 832 mm | 277 W/K | 302 L |
| 4 | 524 mm | 673 W/K | 302 L |
| 8 | 416 mm | 1042 W/K | 302 L |
| 16 | 330 mm | 1603 W/K | 302 L |
Same fluid volume, 5.8× the cooling. ChipVat should be a rack of small vessels, not one large one — and that also keeps each unit under the 272 kg cart limit, which a 640 mm vessel already blows through at ~730 kg.
Assumptions, none of them measured: coolant-side film 3000 W/m²K, a fin-spreading factor of 3 where the tube meets the shell, steel at 16 W/mK. Move the power and coolant sliders to test sensitivity.
Rhombic dodecahedra fill space with no voids. That is the property that makes them attractive — and taken literally it is fatal, because no voids means no coolant. At zero gap the twelve faces of every interior module are in contact with a neighbour, and not one of the boards is wetted.
So the lattice has to be deliberately expanded. Drag the gap slider from 0 and watch the channel open:
| Lattice gap | Channel | Cell packing | Wetted boards |
|---|---|---|---|
| 0 % | 0.0 mm | 100 % | none — inoperable |
| 5 % | 3.9 mm | 86 % | all 12 |
| 15 % | 11.7 mm | 66 % | all 12 |
| 30 % | 23.3 mm | 46 % | all 12 |
The interesting part for a claim is that the gap is not slack — it is a sized coolant channel produced by expanding a space-filling lattice, and its width is set by the buoyancy-driven flow the pumpless architecture depends on. Channel dimension as a claimed function of the module polyhedron is not in any of the three filings.
Aspect W ties the charge to the rating: take the densest charge whose isochore still clears the rating at the junction limit. Push the rating up and you may take more charge. But heat transfer peaks and then falls.
| Rating | Max charge | P at 35 °C | Flux capability |
|---|---|---|---|
| 150 bar | 386 kg/m³ | 79.5 bar | 1.57 W/cm² |
| 250 bar | 651 kg/m³ | 88.6 bar | 2.18 W/cm² |
| 350 bar | 763 kg/m³ | 118 bar | 6.24 W/cm² |
| 500 bar | 856 kg/m³ | 188 bar | 5.61 W/cm² |
| 700 bar | 932 kg/m³ | 306 bar | 4.69 W/cm² |
The peak is aspect X's mechanism showing up as a number. Overcharge and you push the pseudocritical locus out of the boundary layer — the film stops sitting on the cp peak and h drops. The existence of an optimum is robust; its location is not, because the correlation is extrapolated (below).
Servicing means removing the charge. Venting wastes it and releases it. A chilled receiver recovers it with no pump — the charge migrates down its own pressure gradient, which fits the pumpless architecture instead of fighting it.
| Receiver | Pressure | Recovered | Receiver volume |
|---|---|---|---|
| +20 °C | 139 → 57 bar | 81.7 % | 19.6 L |
| 0 °C | 139 → 35 bar | 90.9 % | 16.3 L |
| −20 °C | 139 → 20 bar | 95.3 % | 14.7 L |
Drawn off the top of the closure through a quick disconnect, so the line breaks with the lid and adds no shell penetration — and a leak there vents vapour rather than draining the vessel. The level run means no static head either way.
Every element of SuCCoR's claim 1 (US 11,721,858 B2, in force to ~2041) is marked optional except one: "an outer jacketed vessel around the cooling fluid tank to hold a high thermal conductivity and high specific heat fluid."
You clear that patent on that single element. A water jacket — which I recommended twice before reading the claim — reads straight onto it. Reject heat with a brazed coil, external fins, or a remote plate exchanger. All three work thermally; only the jacket infringes.
The inherent-pressure-bound aspect shows no process upset can overpressure the vessel — the isochore tops out when the silicon reaches its junction limit and stops dissipating. Move the junction-limit slider and watch the fault pressure track it.
External fire is not bounded that way. A rupture disc sized for the fire case is code-required and appears nowhere in the filings.
Keyboard, mouse and monitor never cross the boundary. One or two hermetic optical penetrations plus a 400 V DC power feedthrough sit in the closure; everything fans out to standard ports on the cold side. At 400 V, 12 kW is 30 A — at 48 V it would be 250 A and a far harder penetration.